1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to forming a transistor upon a semiconductor substrate in which the gate is coupled to the substrate to enhance performance of the transistor.
2. Description of the Relevant Art
Fabrication of a MOSFET device is well known. Generally speaking, MOSFETs are manufactured by placing an undoped polycrystalline ("polysilicon") material over a relatively thin gate oxide. The polysilicon material and the gate oxide are then patterned to form a gate conductor with source/drain regions adjacent to and on opposite sides of the gate conductor. The gate conductor and source/drain regions are then implanted with an impurity dopant species. If the impurity dopant species used for forming the source/drain regions is n-type, then the resulting MOSFET is an NMOSFET ("n-channel") transistor device. Conversely, if the source/drain dopant species is p-type, then the resulting MOSFET is a PMOSFET ("p-channel") transistor device. Integrated circuits utilize either n-channel devices exclusively, p-channel devices exclusively, or a combination of both on a single substrate. While both types of devices can be formed, the devices are distinguishable based on the dopant species used.
Because of the increased desire to build faster and more complex integrated circuits, it has become necessary to form relatively small, closely spaced multiple transistors within a single integrated circuit. Unfortunately, as device dimensions shrink, problems associated with subthreshold current, 1.sub.Dst, become paramount. Subthreshold current is current flowing between the drain and source of a transistor when the device is turned off and the gate-to-source voltage, V.sub.GS, of the transistor is less than the absolute value of the transistor threshold voltage, V.sub.T. Ideally, no current flows between the drain and source if V.sub.GS is less than .vertline.V.sub.T .vertline., however, this is not the case when V.sub.GS approaches V.sub.T. Even relatively small values of I.sub.Dst can adversely affect the performance of a device. For example, subthreshold current can leak to and from the output node of each logic cell of a dynamic circuit (e.g., sequential, clocked circuit), and thereby prevent output signals from achieving and maintaining the desired V.sub.DD and V.sub.ss values. The dynamic circuit may even fail if data become lost because of the leaking current. The presence of subthreshold current flow can also add undesirable power consumption in static circuits employed in, for example, combinational logic.
Short-channel effects ("SCE") which can cause the values of I.sub.Dst to increase are related to devices of sub-micron dimensions. Two of the main SCE which affect the values of I.sub.Dst are punchthrough and drain-induced barrier lowering. Punchthrough is normally observed when V.sub.GS is well below V.sub.T. It occurs as a result of the widening of the drain depletion region when the reverse-bias voltage on the drain is increased. The electric field of the drain may eventually penetrate into the source region, and thereby reduce the potential energy barrier of the source-to-body junction. As a result, majority carriers in the source region may gain enough energy to overcome the barrier, leading to an increased current flow from the source to the body. Some of this punchthrough current may be collected by the drain, causing an increase in I.sub.Dst. Similarly, the application of a drain voltage to a short-channel device can lead to drain-induced barrier lowering ("DIBL"). The drain voltage can cause the potential energy barrier at the substrate surface to be lowered, resulting in an increase in I.sub.Dst in the channel region at the gate oxide/substrate interface. As V.sub.GS approaches V.sub.T, the subthreshold current at the surface due to DIBL becomes larger.
It is therefore desirable to develop a technique for fabricating an integrated circuit which can quickly transistion between logic states (i.e., operate at high frequencies) without incurring subthreshold current, I.sub.Dst. Reducing the switching speed (from off to on and vice versa) of the logic gates of an integrated circuit is necessary to more quickly receive a response from an integrated circuit. Unfortunately, for ULSI devices, even a small value of leakage current per device may not be tolerable. Sacrificing device reliability for smaller device dimensions is not a viable option. Thus, it would be beneficial to form an integrated circuit in which source-to-drain current flow does not occur even when device dimensions are reduced and switching speeds are increased.